Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a circuit for training and correcting phases of a write clock and a write data applied to a semiconductor memory device and a method thereof.
A semiconductor memory device stores data in a system composed of a plurality of semiconductor devices. When a data processing apparatus, such as a memory control unit (MCU), requests data, the semiconductor memory device outputs a data corresponding to an address inputted from an apparatus requesting the data, or stores a data provided by the data requesting apparatus at a location corresponding to the address.
Meanwhile, when an operation temperature of a semiconductor system is altered or an operation power is changed while a data is transferred between the data processing apparatus and the semiconductor memory device, there may be a concern regarding the phase of a data inputted/outputted between the data processing apparatus and the semiconductor memory device.
To be specific, the data inputted/outputted between the data processing apparatus and the semiconductor memory device is inputted/outputted in synchronization with a clock for transferring the data. When the operation temperature of the semiconductor system is altered or an operation power is changed while the data is inputted/outputted between the data processing apparatus and the semiconductor memory device, the phase of the data inputted/outputted between the data processing apparatus and the semiconductor memory device and the phase of a clock for transferring the data may differ, and thus, a data having a different phase from the phase of the data at a moment when the data begins being transferred may be outputted. As a result, the data inputted/outputted between the data processing apparatus and the semiconductor memory device may be recognized in a state of being shifted backward or forward by one space from an intended state, which may raise concern. In other words, the data may not be transferred normally.
For example, a process where a data is transferred from the data processing apparatus to the semiconductor memory device will be described. Although a data begins to be transferred to the semiconductor memory device in synchronization with the center of a clock for transferring the data from the data processing apparatus, if the operation temperature of the semiconductor system is altered or the operation power is changed, the phase of the data may be changed to be different from the phase of the clock for transferring the data during the data transferring process. Therefore, the data received by the semiconductor memory device is not synchronized with the center of the clock for transferring the data and may be of a state shifted a little bit to the right/left, and thus the data inputted/outputted between the data processing apparatus and the semiconductor memory device may be recognized in a state shifted backward or forward by one space from an intended state, which may raise concern.
The above-described concern may become more serious as the transmission frequency of the data inputted/outputted between the data processing apparatus and the semiconductor memory device increases. This is because as the transmission frequency of the data inputted/outputted between the data processing apparatus and the semiconductor memory device increases, the length of a data window of the transferred data decreases. Therefore, when the operation temperature of the semiconductor system is altered or the operation power is changed, the data inputted/outputted between the data processing apparatus and the semiconductor memory device may be recognized in a state of being shifted backward or forward by one space from an intended state.